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Research Papers on Vedic Maths

26 May, 2011

1.A hierarchical design of high performance 8x8 bit multiplier based on Vedic mathematics,Sumit R. Vaidya,Deepak R. Dandekar

In this paper, low power and high speed 8x8 Bit Vedic Multiplier is presented. A Novel technique for digit multiplication is produced that is quite different from the conventional method of multiplication like Add and Shift [1]. This paper presents a systematic design methodology for fast and delay efficient Vedic Multiplier based on Vedic Mathematics [2]. The multiplier architecture based on the Vertical and Crosswise algorithm of Ancient Indian Vedic Mathematics. In this paper, general technique for NxN multiplication is proposed and implemented; this gives less delay for calculating the multiplication results for 8x8 Bit Vedic Multiplier. In this paper, less delay and high speed 8x8 Bit Vedic Multiplier is presented. The multiplier cell of the adder is designed by using Pass Transistor (n-transistor), p-transistor used as cross coupled devices. The 8x8 Bit Vedic Multiplier circuit has been simulated using Microwind 3.1 VLSI Layout CAD tools. Simulated results for proposed 8x8 bit Vedic Multiplier circuit shows a great reduction in delay for 0.18 μm.

http://portal.acm.org/citation.cfm?id=1948020

2. Performance Evaluation and Synthesis of Multiplier Used in FFT Operation Using Conventional and Vedic Algorithms Laxman P. Thakre, Suresh Balpande, Umesh Akare, Sudhir Lande

New telecommunication systems are based more than ever before on digital signal processing. High speed digital telecommunication systems such as OFDM and DSL need real-time high-speed computation of the Fast Fourier Transform. Thus there is a need of innovative algorithms to improve the speed. In this paper, we propose vedic algorithm for the implementation of multipliers to be used in the FFT. Vedic mathematics (VM) comes with the simplest and effective algorithm for solving any typical engineering problem standing on the pillars of the “Vedic” principles. The conventional multiplication method requires more time & area on silicon than vedic algorithms. More importantly processing speed increases with the bit length. This will help ultimately to speed up the signal processing task, as it is well known that the multiplier is the basic building block of FFT. The VM has been synthesized for the target device 5vlx30ff324-3.

http://www.computer.org/portal/web/csdl/doi/10.1109/ICETET.2010.57
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